Termination Regulator for DDR-SDRAMs - BD3533F
BD3533F is a termination regulator that complies with JEDEC requirements for DDR-SDRAM. This linear power supply uses a built-in N-channel MOSFET and high-speed OP-AMPS specially designed to provide excellent transient response. It has a sink/source current capability up to 1A and has a power supply bias requirement of 3.3V to 5.0V for driving the N-channel MOSFET. By employing an independent reference voltage input (VDDQ) and a feedback pin (VTTS), this termination regulator provides excellent output voltage accuracy and load regulation as required by JEDEC standards. Additionally, BD3533 has a reference power supply output (VREF) for DDR-SDRAM or for memory controllers. Unlike the VTT output that goes to "Hi-Z" state, the VREF output is kept unchanged when EN input is changed to "Low", making this IC suitable for DDR-SDRAM under "Self Refresh" state.
| Part Number | Status | Package | Unit Quantity | Minimum Package Quantity | Packing Type | RoHS |
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| BD3533F-E2 | Active | SOP8 | 2500 | 2500 | Taping | Yes |
BD3533F Data Sheet
Specifications| Grade | Standard | | ch | 1 | | Vin(Min.)[V] | 2.7 | | Vin(Max.)[V] | 5.5 | | Vout (Typ.) [V] | 0.75 to 1.25 | | Iout(Max.)[A] | 3.0 | | Thermal Shut-down | Yes | | Under Voltage Lock Out | Yes | | Operating Temperature (Min.)[°C] | -20 | | Operating Temperature (Max.)[°C] | 100 |
| Technical Documents |
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