Feature| Description | 32-bit microcontroller based on highly functional ARM926EJ-S™ core incorporating
Multi-layer internal bus |
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| RoHS Compatible Product(s) (#) | Available |
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Package Information| Package Image |  |
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| Toshiba Package Name | FBGA361-P-1616-0.80AZ |
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| Pins | 361 |
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| Mounting | Surface Mount |
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| Description| Property | Value | Unit |
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| group name | A910 | - | | number of bits | 32 | bit | | ROM type | ROM less | - | | RAM size | 56 | Kbyte | | USB Device (High Speed) | 1 | ch | | UART | 2 | ch | | I2C | 2 | ch | | Sync. Serial Interface | 2 | ch | | DMA controllers | 8 | ch | | Static Memory Controller | 4 | ch | | DRAM Controller (With Support for SDR SDRAMs and LVCMOS DDR SDRAMs) | 1 | ch | | NANDFC | 2 | ch | | A/D converters(10bit) | 6 | ch | | LCD controller | Available | - | | LCD Data Process Accelerator | Available | - | | External Address Space(bytes) | 64M | byte | | Internal Address Space(bytes) | 4G | byte | | clock_output | 2 | ch | | Timer/counter(16bit) | 6 | ch | | clock timer | Available | - | | watchdog timer | Available | - | | I2S (Inter-IC Sound) Interface | 2 | ch | | Touch Screen Interface | Available | - | | CMOS Image Sensor Interface | 1 | ch | | JTAG (Boundary-Scan) | Available | - | | JTAG (Debug) | Available | - | | Clock gear function | Available | - | | internal data bus width | 32 | bit | | external data bus width | 32 | bit | | I/O Port | 114 | port |
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