数据手册：DS21348, DS21Q348 .pdf [英文Rev.4(PDF,792kB)]
{状况：生产中。详细情况请参考订购信息。}
The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build-outs or CSU line build-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8).
The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-
bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an
8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all
of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,
JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
产品关键特性
- Complete E1, T1, or J1 line interface unit (LIU)
- Supports both long-haul and short-haul trunks
- Internal software-selectable receive-side termination for 75Ω/100Ω/120Ω
- 3.3V power supply
- 32-bit or 128-bit crystal-less jitter attenuator requires only a 2.048MHz master clock for both E1 and T1 with option to use 1.544MHz for T1
- Generates the appropriate line build-outs, with and without return loss, for E1 and DSX-1 and CSU line build-outs for T1
- AMI, HDB3, and B8ZS, encoding/decoding
- 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered clock
- Programmable monitor mode for receiver
- Loopbacks and PRBS pattern generation/detection with output for received errors
- Generates/detects in-band loop codes, 1 to 16 bits including CSU loop codes
- 8-bit parallel or serial interface with optional hardware mode
- Muxed and nonmuxed parallel bus supports Intel or Motorola
- Detects/generates blue (AIS) alarms
- NRZ/bipolar interface for TX/RX data I/O
- Transmit open-circuit detection
- Receive carrier loss (RCL) indication (G.775)
- High-Z state for TTIP and TRING
- 50mA (rms) current limiter
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原理框图
芯片订购型号
| 订购型号 | 产品状态 | 封装形式 | 工作温度 | RoHS/无铅 |
| DS21348G | | 生产中 | | CSBGA；49引脚；CSBGA；49引脚封装信息 |
| DS21348G+ | | 生产中 | | L-FPBGA-OM-LF；49引脚；CSBGA；49引脚封装信息 |
| DS21348GN | | 生产中 | | CSBGA；49引脚；CSBGA；49引脚封装信息 |
| DS21348GN+ | | 生产中 | | L-FPBGA-OM-LF；49引脚；CSBGA；49引脚封装信息 |
| DS21348T | N/A | 停止供货 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348T+ | | 生产中 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348T-W | N/A | 停止供货 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348TB | N/A | 停止供货 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348TN | | 限制供货 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348TN+ | | 生产中 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21348TNB | N/A | 停止供货 | | TQFP；44引脚；148.8mm²封装信息 |
| DS21Q348 | N/A | 停止供货 | DS21448G | BGA；144引脚封装信息 |
| DS21Q348N | N/A | 停止供货 | DS21448G | BGA；144引脚封装信息 |
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