74ALVT162823: 具有复位和使能功能、带30 Ohm终端电阻的18位总线接口D型触发器(三态)

74ALVT162823 18位总线接口寄存器设计用于取消缓冲现有寄存器所需的额外封装,并提供额外数据宽度,用于总线进行奇偶校验的更宽数据/地址路径。

74ALVT162823具有带时钟使能(nCE) 和主复位(nMR) 的两个9位宽缓冲寄存器,它们非常适合用于高微编程系统中的奇偶校验总线连接。

这些寄存器为完全边沿触发。在时钟从低到高转换前的某个建立时间,每个D输入状态都会被传输到相应的触发器Q输出。

74ALVT162823设计在上拉和下拉输出结构中使用30 Ω串联电阻。该设计可降低存储器地址驱动器、时钟驱动器以及总线接收器/发送器等应用中的线路噪声。

74ALVT162823: 产品结构框图
Outline 3d SOT364-1
数据手册 (1)
名称/描述Modified Date
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state (REV 2.0) PDF (116.0 kB) 74ALVT162823 [English]11 Aug 2005
应用说明 (8)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
手册 (2)
名称/描述Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]15 Apr 2013
支持信息 (1)
名称/描述Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态
74ALVT162823DGGActive
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74ALVT162823DGGSOT364-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1 in DrypackActive74ALVT162823DGGY (9352 616 58518)ALVT16282374ALVT162823DGGAlways Pb-free70.81.337.52E822
Tube in DrypackActive74ALVT162823DGGS (9352 616 58512)ALVT16282374ALVT162823DGGAlways Pb-free70.81.337.52E822
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state 74ALVT162823DGG
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
alvt162823 IBIS model 74ALVT162823DGG
alvt16 Spice model 74ALVT16827DL
plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
74ALVT162823
74LVT16652A