74LVCH32374AEC：带5 V容压输入/输出的32位边沿触发D型触发器（三态）

74LVCH32374A是32位边沿触发式触发器，具有用于每个触发器的独立D类输入以及用于总线应用的三态输出。该器件由8个边沿触发式触发器的4部分组成。每个8位部分都具有一个时钟（引脚nCP）输入和一个输出使能输入（引脚nOE）。触发器会存储它们各自的D输入状态，满足nCP从低到高转换的建立和保持时间要求。引脚nOE为低电平时，触发器的内容在输出处可用。引脚nOE为高电平时，输出会进入高阻抗关断状态。引脚nOE的操作不会影响触发器的状态。输入可从3.3 V器件或5 V器件驱动。在三态操作中，输出可处理5 V。这些特性允许在混合3.3 V或5 V环境中使用这些器件。

总线保持数据输入无需用外部上拉电阻来保持闲置输入。

特性和优势
    • 与5 V逻辑器件连接的5 V容压输入/输出
    • 1.2 V至3.6 V的宽电源电压范围
    • CMOS低功耗
    • MULTIBYTE直通标准引脚排列架构
    • 用于最大程度减少噪声和接地反弹的多个低电感电源引脚
    • 直接与TTL电平连接
    • 所有数据输入都有总线保持
    • 高阻抗（VCC = 0 V时）
    • 根据JESD 78 II类，锁存性能超过500 mA
    • 符合JEDEC标准：
      • JESD8-7A（1.65 V至1.95 V）
      • JESD8-5A（2.3 V至2.7 V）
      • JESD8-C/JESD36（2.7 V至3.6 V）
    • JESD8-7A（1.65 V至1.95 V）
    • JESD8-5A（2.3 V至2.7 V）
    • JESD8-C/JESD36（2.7 V至3.6 V）
    • ESD保护：
      • HBM JESD22-A114F超过2000 V
      • MM JESD22-A115-B超过200 V
      • CDM JESD22-C101E超过1000 V
    • HBM JESD22-A114F超过2000 V
    • MM JESD22-A115-B超过200 V
    • CDM JESD22-C101E超过1000 V
    • 指定温度范围为-40 °C至+85 °C和-40 °C至+125 °C
    • 采用塑料细距球栅阵列封装
产品图片
功能框图
Block diagram: 74LVCH32374AEC
关键参数
型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74LVCH32374AECProduction1.2 - 3.6CMOS/LVTTL+/- 243.8150low-40~1256016.0LFBGA96
封装与包装
型号封装Outline versionReflow-/Wave soldering包装产品状态标示可订购的器件编号, (订购码 (12NC))
74LVCH32374AEC
LFBGA96
(SOT536-1)		sot536-1_posot536-1_frReel 13" Q1/T1 in Drypack量产CH32374A74LVCH32374AEC,518( 9352 644 49518 )
Tray, Bakeable, Multiple in Drypack量产CH32374A74LVCH32374AEC,557( 9352 644 49557 )
Tray, Bakeable, Single in Drypack量产CH32374A74LVCH32374AEC,551( 9352 644 49551 )
74LVCH32374AEC/G
LFBGA96
(SOT536-1)		sot536-1_posot536-1_frReel 13" Q1/T1 in Drypack量产CH32374A74LVCH32374AEC/G,5( 9352 811 42518 )
Tray, Bakeable, Multiple in Drypack量产CH32374A74LVCH32374AEC/G;5( 9352 811 42557 )
Tray, Bakeable, Single in Drypack量产CH32374A74LVCH32374AEC/G:5( 9352 811 42551 )
无铅环保信息
型号可订购的器件编号RoHS / RHF无铅转换日期EFRIFR (FIT)MTBF（小时）潮湿敏感度等级MSL LF
74LVCH32374AEC74LVCH32374AEC,518123.83.872.58E834
74LVCH32374AEC74LVCH32374AEC,557123.83.872.58E834
74LVCH32374AEC74LVCH32374AEC,551123.83.872.58E834
74LVCH32374AEC/G74LVCH32374AEC/G,5Always Pb-free123.83.872.58E8NA2
74LVCH32374AEC/G74LVCH32374AEC/G;5Always Pb-free123.83.872.58E8NA2
74LVCH32374AEC/G74LVCH32374AEC/G:5Always Pb-free123.83.872.58E8NA2
文档资料
档案名称标题类型格式日期
74LVCH32374A (中文)32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-stateData sheetpdf2012-12-18
AN240Interfacing 3 Volt and 5 Volt ApplicationsApplication notepdf1995-09-15
AN263Power considerations when using CMOS and BiCMOS logic devicesApplication notepdf2002-02-05
AN11009Pin FMEA for LVC familyApplication notepdf2011-02-04
AN1026(LF)BGA Application note, ATO InnovationApplication notepdf2013-03-13
ANLFBGAANLFBGA 32-Bit Logic Families in Low-profile Fine-pitch Ball Grid Array (LFBGA) PackagesApplication notepdf2013-03-13
AN212Package lead inductance considerations in high-speed applicationsApplication notepdf2013-03-13
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
75017668Low voltage CMOS family - LVCBrochurepdf2015-07-10
lvch32374alvch32374a IBIS modelIBIS modelibs2013-04-07
75017285Logic selection guide 2015Selection guidepdf2015-01-08
sot536-1_poplastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mmOutline drawingpdf2009-10-08
sot536-1_frFootprint for reflow soldering SOT536-1Reflow solderingpdf2009-10-08
订购信息
型号订购码 (12NC)可订购的器件编号
74LVCH32374AEC9352 644 4951874LVCH32374AEC,518
74LVCH32374AEC9352 644 4955774LVCH32374AEC,557
74LVCH32374AEC9352 644 4955174LVCH32374AEC,551
74LVCH32374AEC/G9352 811 4251874LVCH32374AEC/G,5
74LVCH32374AEC/G9352 811 4255774LVCH32374AEC/G;5
74LVCH32374AEC/G9352 811 4255174LVCH32374AEC/G:5
模型
标题类型日期
lvch32374a IBIS modelIBIS model2013-04-07
32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state 74LVCH32374AEC
74LVCH32374AEC
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Pin FMEA for LVC family 74LVC1G123_Q100
(LF)BGA Application note, ATO Innovation 74LVC_H_16245A_Q100
ANLFBGA 32-Bit Logic Families in Low-profile Fine-pitch Ball Grid Array (LFBGA) Packages 74LVC_H_16245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Low voltage CMOS family - LVC 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm 74LVTH32245EC
Footprint for reflow soldering SOT536-1 74LVTH32245EC
lvch32374a IBIS model 74LVCH32374AEC
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