MC100E143: ECL 9-Bit Hold Register
The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0-D8 accepting parallel input data. The SEL (Select) input pin is used to switch between the two modes of operation HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.The 100 Series contains temperature compensation.
特性- 700MHz Min. Operating Frequency
- 9-Bit for Byte-Parity Applications
- Asynchronous Master Reset
- Dual Clocks
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- 75kW Input Pulldown Resistors
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors
- ESD Protection: > 2 KV HBM, > 200 V MM
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
- Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
- Transistor Count = 484 devices
- Pb-Free Packages are Available
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应用注释 (18)
数据表 (1)
仿真模型 (1)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| 28 LEAD PLCC | 776-02 (67.7kB) | F |
产品订购型号
| 产品 | 状况 | Compliance | 具体说明 | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| MC100E143FNG | Active | Pb-free
Halide free | ECL 9-Bit Hold Register | PLCC-28 | 776-02 | 3 | Tube | 37 | 联系BDTIC |
| MC100E143FNR2G | Active | Pb-free
Halide free | ECL 9-Bit Hold Register | PLCC-28 | 776-02 | 3 | Tape and Reel | 500 | 联系BDTIC |
订购产品技术参数
| Product | Type | Bits | Input Level | Output Level | VCC Typ (V) | tJitter Typ (ps) | tpd Typ (ns) | tsu Min (ns) | th Min (ns) | trec Typ (ns) | tR & tF Max (ps) | fToggle Typ (MHz) |
|---|
| MC100E143FNG | Register | 9 | ECL | ECL | 5 | 1 | 0.8 | 0.05 | 0.3 | 0.7 | 800 | |
| MC100E143FNR2G | Register | 9 | ECL | ECL | 5 | 1 | 0.8 | 0.05 | 0.3 | 0.7 | 800 | |
