MC100EL12: 5.0 V ECL Low Impedance Driver

The MC10EL/100EL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is a function equivalent to the E112 device with higher performance capabilities. With propagation delays significantly faster than the E112 the EL12 is ideally suited for those applications which require the ultimate in AC performance.The 100 Series contains temperature compensation.

特性
  • 290ps Propagation Delay
  • Dual Outputs for 25W Drive Applications
  • ESD Protection: > 1 KV HBM, > 100 V MM
  • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 44 devices
  • Pb-Free Packages are Available
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (66kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL Low Impedance DriverMC10EL12/D (127.0kB)7
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EL12D VEE -5.2 VMC100EL12D.IBS (8.0kB)2
IBIS Model for MC100EL12DPECL - Positive ECLMC100EL12DPECL.IBS (8.0kB)
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价）
MC100EL12DGActivePb-free5.0 V ECL Low Impedance DriverSOIC-8751-071Tube98联系BDTIC
MC100EL12DR2GActivePb-free5.0 V ECL Low Impedance DriverSOIC-8751-071Tape and Reel2500联系BDTIC
MC100EL12DTGActivePb-free Halide free5.0 V ECL Low Impedance DriverTSSOP-8948R-023Tube100联系BDTIC
MC100EL12DTR2GActivePb-free Halide free5.0 V ECL Low Impedance DriverTSSOP-8948R-023Tape and Reel2500联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EL12DGSignal Driver11:1ECLECL50.295501000
MC100EL12DR2GSignal Driver11:1ECLECL50.295501000
MC100EL12DTGSignal Driver11:1ECLECL50.295501000
MC100EL12DTR2GSignal Driver11:1ECLECL50.295501000
5V ECL Low Impedance Driver MC10EL12
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EL12D VEE -5.2 V MC100EL12
IBIS Model for MC100EL12DPECL - Positive ECL MC100EL12
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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