MC100EP105: ECL Quad 2-Input Differential AND/NAND Gate

The MC10/100EP105 is a quad 2-input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available.The 100 Series contains temperature compensation.

特性
  • 275ps Typical Propagation Delay
  • Maximum Frequency > 3 Ghz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Pb-Free Packages are Available
应用
  • General Purpose Logic
封装
应用注释 (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL Quad 2-Input Differential AND/NANDMC10EP105/D (160.0kB)11
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EP105FAGActivePb-free Halide freeLQFP-32联系BDTIC2Tray JEDEC250联系BDTIC
MC100EP105FAR2GActivePb-free Halide freeLQFP-32联系BDTIC2Tape and Reel2000联系BDTIC
MC100EP105MNGLast ShipmentsPb-free Halide freeQFN-32488AM1Tube74
MC100EP105MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
订购产品技术参数
ProductTypeChannelsInput LevelOutput LevelVCC Typ (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100EP105FAGAND/NAND1ECL CMLECL5 3.330000.2750.2200
MC100EP105FAR2GAND/NAND1ECL CMLECL5 3.330000.2750.2200
3.3V / 5V ECL Quad 2-Input Differential AND/NAND (160.0kB) MC10EP105
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804