MC100EP11: Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V

The MC10EP11 is a differential 1 to 2 fanout buffer. The device is pin and functionally equivalent to the LVEL11 device. With AC performance much faster than the LVEL11 device, the EP11 is ideal for applications requiring the fastest AC performance available.

特性
  • 220 ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Outputs Will Default LOW with Inputs Open or at VEE
封装
应用注释 (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL 1:2 Differential Fanout BufferMC10EP11/D (185kB)11Jul, 2016
仿真模型 (5)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP11DT -3.3VMC100EP11DT_-33.IBS (5.0kB)2
IBIS Model for MC100EP11DT 3.3MC100EP11DT_33.IBS (5.0kB)2
IBIS Model for MC100EP11DT at -5.0VMC100EP11DT_-50.IBS (5.0kB)1
IBIS Model for mc100ep11d 3.3VMC100EP11D_33.IBS (5.0kB)1
IBIS Model for mc100ep11dt 5.0VMC100EP11DT_50.IBS (5.0kB)2
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EP11DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100EP11DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100EP11DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100EP11DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100EP11MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
MC100EP11MNTAGActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP11DGBuffer11:2CML ECLECL5 3.30.2150.221703000
MC100EP11DR2GBuffer11:2CML ECLECL5 3.30.2150.221703000
MC100EP11DTGBuffer11:2CML ECLECL3.3 50.2150.221703000
MC100EP11DTR2GBuffer11:2CML ECLECL3.3 50.2150.221703000
MC100EP11MNR4GBuffer11:2ECL CMLECL3.3 50.2150.221703000
MC100EP11MNTAGBuffer11:2ECL CMLECL3.3 50.2150.221703000
3.3 V / 5 V ECL 1:2 Differential Fanout Buffer (185kB) MC10EP11
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP11DT -3.3V MC100EP11
IBIS Model for MC100EP11DT 3.3 MC100EP11
IBIS Model for MC100EP11DT at -5.0V MC100EP11
IBIS Model for mc100ep11d 3.3V MC100EP11
IBIS Model for mc100ep11dt 5.0V MC100EP11
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220