MC100EP196: 3.3 V ECL Programmable Delay Chip
The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
特性
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封装
应用注释 (14)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
| Designing with PECL (ECL at +5.0 V) | AN1406/D (105.0kB) | 2 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide | AND8002 (71kB) | 12 | |
| Interfacing Between LVDS and ECL | AN1568/D (121.0kB) | 11 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Phase Lock Loop General Operations | AND8040/D (64.0kB) | 3 | |
| Storage and Handling of Drypack Surface Mount Device | AND8003/D (49kB) | 2 | Mar, 2016 |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 | |
| Thermal Analysis and Reliability of WIRE BONDED ECL | AND8072/D (119.0kB) | 5 | |
| Using Wire-OR Ties in ECLInPS™ Designs | AN1650/D (1130.0kB) | 3 |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3V ECL Programmable Delay Chip with FTUNE | MC100EP196/D (145kB) | 16 |
仿真模型 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for MC100EP196FA | MC100EP196FA_33V_ECL.IBS (0.0kB) |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100EP196FAG | Active | Pb-free Halide free | LQFP-32 | 联系BDTIC | 2 | Tray JEDEC | 250 | 联系BDTIC |
| MC100EP196FAR2G | Active | Pb-free Halide free | LQFP-32 | 联系BDTIC | 2 | Tape and Reel | 2000 | 联系BDTIC |
订购产品技术参数
| Product | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | td(prog) Min (ns) | td(prog) Max (ns) | td(step) Typ (ps) | tJitter Typ (ps) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|---|---|
| MC100EP196FAG | CML ECL | ECL | 3.3 | 1200 | 8.6 | 12 | 11 | 3 | 200 |
| MC100EP196FAR2G | ECL CML | ECL | 3.3 | 1200 | 8.6 | 12 | 11 | 3 | 200 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for MC100EP196FA MC100EP196B
