MC100EP57: Multiplexer, 4:1 Differential, ECL, 3.3 V / 5.0 V _ BDTIC 中国领先电子元器件代理商

MC100EP57: Multiplexer, 4:1 Differential, ECL, 3.3 V / 5.0 V

The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution.The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).Multiple VBB outputs are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.

特性

375 ps Typical Propagation Delays
Maximum Frequency > 2 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
VBB Outputs
Useful as Either 4:1 or 2:1 Multiplexer
These are Pb-Free Devices

应用

Ideal for use in low skew applications such as clock distribution

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V/5V ECL 4:1 Differential Multiplexer	MC10EP57/D (107kB)	13

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP57DT 3.3V	MC100EP57DT_33.IBS (11.0kB)	4
IBIS Model for MC100EP57DT with VEE at -5.2 V	MC100EP57DT_-52.IBS (11.0kB)	1

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN20, 4x4, 0.5P	485E-01 (60.9kB)	B
TSSOP-20 WB	948E-02 (39.7kB)	D

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP57DTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	联系BDTIC
MC100EP57DTR2G	Active	Pb-free	TSSOP-20	948E-02	1	Tape and Reel	2500	联系BDTIC
MC100EP57MNG	Active	Pb-free Halide free	QFN-20	485E-01	1	Tube	92	联系BDTIC
MC100EP57MNTXG	Lifetime	Pb-free Halide free	QFN-20	485E-01	1	Tape and Reel	3000