MC100EP58: Multiplexer, 2:1 Differential, ECL, 3.3 V / 5.0 V _ BDTIC 中国领先电子元器件代理商

MC100EP58: Multiplexer, 2:1 Differential, ECL, 3.3 V / 5.0 V

The MC10EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices.

特性

310ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
Open Input Default State
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

封装

MC100EP58 封装

应用注释 (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5 V ECL 2:1 Multiplexer	MC10EP58/D (164kB)	8	Aug, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc100ep58dt 3.3	MC100EP58DT_33.IBS (6.0kB)	2

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP58DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100EP58DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100EP58DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EP58DTR2G	Lifetime	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500

订购产品技术参数

Product	Input/Output Ratio	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tJitter Typ (ps)	tskew(OO) Max (ps)	tpd Typ (ns)
MC100EP58DG	2:1	1	CML ECL	ECL	3.3 5	3000	0.2		0.31
MC100EP58DR2G	2:1	1	ECL CML	ECL	3.3 5	3000	0.2		0.31
MC100EP58DTG	2:1	1	ECL CML	ECL	5 3.3	3000	0.2		0.31

3.3 V / 5 V ECL 2:1 Multiplexer (164kB) MC100EP58

AC Characteristics of ECL Devices NB100LVEP91

Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91

Designing with PECL (ECL at +5.0 V) NB100LVEP91

ECL Clock Distribution Techniques NB100LVEP91

ECLinPS Plus™ Spice Modeling Kit MC10EPT20

ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91

Interfacing Between LVDS and ECL NB100ELT23L

Interfacing with ECLinPS NB100LVEP91

Metastability and the ECLinPS Family MC10EPT20

Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201

Phase Lock Loop General Operations MC10H604

Storage and Handling of Drypack Surface Mount Device NB3U23C

Termination of ECL Logic Devices NB100LVEP91

The ECL Translator Guide NB100LVEP91

Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91

Using Wire-OR Ties in ECLInPS™ Designs MC10H351

IBIS Model for mc100ep58dt 3.3 MC100EP58

SOIC-8 Narrow Body CM1216

TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L

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