MC100LVEL34: 3.3 V ECL ÷·2, ÷·4, ÷·8 Divider

The MC100LVEL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (EN bar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulsecould lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start−up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internaldividers, as well as multiple LVEL34s in a system.

特性
  • 50 ps Typical Output-to-Output Skew
  • Synchronous Enable/Disable
  • Master Reset for Synchronization
  • 1.5 GHz Toggle Frequency
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
  • Open Input Default State
  • LVDS Input Compatible
  • Pb-Free Packages are Available
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V ECL /2, /4, /8 Clock Generation ChipMC100LVEL34/D (93kB)4Apr, 2014
仿真模型 (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEP34D 3.3VMC100LVEP34D_33.IBS (10.0kB)1
IBIS Model for MC100LVEP34DT 3.3VMC100LVEP34DT_33.IBS (10.0kB)1
IBIS Model for MC100lvel34dt at 3.3VMC100LVEL34DT_33.IBS (9.0kB)1
IBIS Model for mc100lvel34d at 3.3VMC100LVEL34D_33.IBS (10.0kB)1
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC 16 LEAD751B-05 (38.2kB)K
TSSOP-16948F-01 (41.7kB)B
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100LVEL34DGActivePb-freeSOIC-16751B-051Tube48联系BDTIC
MC100LVEL34DR2GActivePb-free Halide freeSOIC-16751B-051Tape and Reel2500联系BDTIC
MC100LVEL34DTGActivePb-free Halide freeTSSOP-16948F-011Tube96联系BDTIC
MC100LVEL34DTR2GActivePb-free Halide freeTSSOP-16948F-011Tape and Reel2500联系BDTIC
订购产品技术参数
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVEL34DGDividerLVDS ECLECL3.315000.7400
MC100LVEL34DR2GDividerLVDS ECLECL3.315000.7400
MC100LVEL34DTGDividerECL LVDSECL3.315000.7400
MC100LVEL34DTR2GDividerECL LVDSECL3.315000.7400
3.3V ECL /2, /4, /8 Clock Generation Chip (93kB) MC100LVEL34
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEP34D 3.3V MC100LVEP34
IBIS Model for MC100LVEP34DT 3.3V MC100LVEP34
IBIS Model for MC100lvel34dt at 3.3V MC100LVEL34
IBIS Model for mc100lvel34d at 3.3V MC100LVEL34
SOIC 16 LEAD MC14504B
TSSOP-16 MC14504B