MC10E131: ECL 4-Bit D Flip-Flop _ BDTIC 中国领先电子元器件代理商

MC10E131: ECL 4-Bit D Flip-Flop

The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using CC to clock all four flip-flops. In this case, the CEbar inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CEbar are LOW, and transfers to the slave when either CC or CEbar (or both) go HIGH.The 100 Series contains temperature compensation.

特性

1100MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
75kW Input Pulldown Resistors
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
Metastability Time Constant is 200 ps.
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
ESD Protection: > 2 KV HBM, > 200 V MM
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 240 devices
Pb-Free Packages are Available

封装

应用注释 (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS™ Circuit Performance at Non-Standard VIH Levels	AN1404/D (51.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3