MC10E142: ECL 9-Bit Shift Register _ BDTIC 中国领先电子元器件代理商

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MC10E142: ECL 9-Bit Shift Register

The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.

特性

700MHz Min. Shift Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
75kW Input Pulldown Resistors
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 KV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 405 devices
Pb-Free Packages are Available

应用注释 (17)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (66kB)	11
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS™ Circuit Performance at Non-Standard VIH Levels	AN1404/D (51.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS™	AND8066/D (58.0kB)	2
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (106.0kB)	1
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
5V ECL 9-Bit Shift Register	MC10E142/D (150.0kB)	7

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc10e142fn 5.0V	MC10E142FN_50.IBS (13.0kB)	3

封装图纸 (1)

Document Title	Document ID/Size	Revision
28 LEAD PLCC	776-02 (67.7kB)	F

产品订购型号

产品	状况	Compliance	具体说明	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10E142FNG	Active	Pb-free Halide free	ECL 9-Bit Shift Register	PLCC-28	776-02	3	Tube	37	联系BDTIC
MC10E142FNR2G	Active	Pb-free Halide free	ECL 9-Bit Shift Register	PLCC-28	776-02	3	Tape and Reel	500	联系BDTIC