MC10E1651: 5.0 V, -5.0 V Dual ECL Output Comparator with Latch

The MC10E1651 comparator is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using the advanced MOSAIC III process. The MC10E1651 comparator incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENabar and LENbbar) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.The 100 series contains temperature compensation.

特性
  • Typical 3.0 dB Bandwidth > 1.0 GHz
  • Typical V to Q Propagation Delay of 775 ps
  • Typical Output Rise/Fall of 350 ps
  • Common Mode Range -2.0 V to +3.0 V
  • Individual Latch Enables
  • Differential Outputs
  • 28mV Input Hysteresis
  • Operating Mode: VCC = 5.0 V, VEE = -5.2 V
  • No Internal Input Pulldown Resistors
  • ESD Protection: > 2 KV HBM, > 100 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 85 devices
封装
应用注释 (7)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS™ Circuit Performance at Non-Standard VIH LevelsAN1404/D (51.0kB)1
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V, -5V ECL Dual ECL Output Comparator With LatchMC10E1651/D (120.0kB)10
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10E1651FNMC10E1651FN.IBS (10.0kB)
封装图纸 (1)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10E1651FNGActivePb-free Halide freePLLC-20775-023Tube46$33.3325
MC10E1651FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500$33.3325
MC10E1651FNLast ShipmentsPLLC-20775-021Tube46
MC10E1651FNR2ObsoletePLLC-20775-021Tape and Reel500
订购产品技术参数
ProductChannelsVCC Min (V)VCC Max (V)IO Typ (mA)ICC Typ (mA)tres Typ (ns)VIO Max (mV)TA Min (°C)TA Max (°C)
MC10E1651FNG2-5.2550550.92525085
MC10E1651FNR2G2-5.2550550.92525085
5V, -5V ECL Dual ECL Output Comparator With Latch (120.0kB) MC10E1651
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS™ Circuit Performance at Non-Standard VIH Levels MC10E195
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
IBIS Model for MC10E1651FN MC10E1651
20 LEAD PLLC MC10H351