MC10EL31: 5.0 V ECL D Flip-Flop with Set and Reset
The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131 the EL31 is ideally suited for those applications which require the ultimate in AC performance. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.The 100 Series contains temperature compensation.
特性
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封装
应用注释 (17)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 5 V ECL D Flip-Flop With Set and Reset | MC10EL31/D (141kB) | 7 | Jul, 2016 |
仿真模型 (2)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for mc10el31d -5.0V | MC10EL31D_-50.IBS (9.0kB) | 1 | |
| IBIS Model for mc10el31d 5.0V | MC10EL31D_50.IBS (9.0kB) | 1 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
| TSSOP 8 3.0x3.0x0.95 mm | 948R-02 (77.3kB) | A |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10EL31DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC10EL31DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
| MC10EL31DTG | Active | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | 联系BDTIC |
订购产品技术参数
| Product | Type | Bits | Input Level | Output Level | VCC Typ (V) | tJitter Typ (ps) | tpd Typ (ns) | tsu Min (ns) | th Min (ns) | trec Typ (ns) | tR & tF Max (ps) | fToggle Typ (MHz) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MC10EL31DG | D-Type | 1 | ECL | ECL | 5 | 1 | 0.475 | 0.15 | 0.25 | 0.2 | 350 | 2800 |
| MC10EL31DR2G | D-Type | 1 | ECL | ECL | 5 | 1 | 0.475 | 0.15 | 0.25 | 0.2 | 350 | 2800 |
| MC10EL31DTG | D-Type | 1 | ECL | ECL | 5 | 1 | 0.475 | 0.15 | 0.25 | 0.2 | 350 | 2800 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for mc10el31d -5.0V MC10EL31
- IBIS Model for mc10el31d 5.0V MC10EL31
- SOIC-8 Narrow Body CM1216
- TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
