MC10EP446: 3.3 V / 5.0 V ECL 8-Bit Differential Parallel to Serial Converter

The MC10/100EP446 is an integrated 8-bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal data rate using the CKSEL pin. Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, VBB pin is provided for single-ended input condition. The 100 Series devices contain temperature compensation network.

特性
  • 3.2 Gb/s Typical Data Rate Capability
  • Differential Clock and Serial Inputs
  • VBB Output for Single-ended Input Applications
  • Asynchronous Data Reset (SYNC)
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Parallel Interface Can Support PECL, TTL and CMOS
  • Pb-Free Packages are Available
应用
  • Parallel to Serial Conversion
封装
应用注释 (9)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Serial / Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data InputMC10EP446/D (185kB)11
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC10EP446FAGActivePb-free Halide freeLQFP-32联系BDTIC2Tray JEDEC250联系BDTIC
MC10EP446FAR2GLifetimePb-free Halide freeLQFP-32联系BDTIC2Tape and Reel2000
MC10EP446MNGLifetimePb-free Halide freeQFN-32488AM1Tube74
MC10EP446MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)fdr Typ (Gb/sec)tpd Typ (ns)tsu Min (ns)th Min (ns)tJitter Typ (ps)tR & tF Max (ps)
MC10EP446FAGParallel/Serial8ECL CMLECL3.3 53.40.8-0.45-0.60.2150
Serial / Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data Input (185kB) MC10EP446
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804
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