MC10H141: 4-Bit Universal Shift Register _ BDTIC 中国领先电子元器件代理商

MC10H141: 4-Bit Universal Shift Register

The MC10H141 is a four-bit universal shift register. This device is a functional/pinout duplication of the standard MECL 10K part with 100% improvement in propagation delay and operation frequency and no increase in power supply current.

特性

Shift frequency, 250 MHz Min
Power Dissipation, 425 mW Typical
Improved Noise Margin 150 mV (over operating voltage and temperature range)
Voltage Compensated
MECL 10K Compatible
Pb-Free Packages are Available

应用注释 (10)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
Family Characteristics for MECL 10H™ and MECL 10K™	TND309/D (248.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12

封装图纸 (2)

Document Title	Document ID/Size	Revision
20 LEAD PLLC	775-02 (60.9kB)	F
PDIP-16	648-08 (34.2kB)	V

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Four-Bit Universal Shift Register	MC10H141/D (137kB)	9	Aug, 2016

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10H141FNR2G	Active	Pb-free Halide free	PLLC-20	775-02	3	Tape and Reel	500	联系BDTIC
MC10H141PG	Last Shipments	Pb-free Halide free	PDIP-16	648-08	NA	Tube	25

订购产品技术参数

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC10H141FNR2G	Shift Register	4	ECL	ECL	-5.2		1.5	1.5	1		2400	250

Four-Bit Universal Shift Register (137kB) MC10H141

AC Characteristics of ECL Devices NB100LVEP91

Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91

Designing with PECL (ECL at +5.0 V) NB100LVEP91

ECL Clock Distribution Techniques NB100LVEP91

Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604

Interfacing Between LVDS and ECL NB100ELT23L

Interfacing with ECLinPS NB100LVEP91

Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201

Termination of ECL Logic Devices NB100LVEP91

The ECL Translator Guide NB100LVEP91

20 LEAD PLLC MC10H351

PDIP-16 MC10H350

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