MC10H176: Hex Master-Slave D Flip-Flop

The MC10H176 contains six master slave type D flip-flops with a common clock. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in clock frequency and propagation delay and no increase in power-supply current.

特性
  • Propagation Delay, 1.7 ns Typical
  • Power Dissipation, 460 mW Typical
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K Compatible
  • Pb-Free Packages are Available
应用注释 (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Hex D Master-Slave Flip-FlopMC10H176/D (153.0kB)7
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价)
MC10H176FNGActivePb-free Halide freeHex Master-Slave D Flip-FlopPLLC-20775-023Tube46联系BDTIC
MC10H176FNR2GActivePb-free Halide freeHex Master-Slave D Flip-FlopPLLC-20775-023Tape and Reel500联系BDTIC
MC10H176PGActivePb-free Halide freeHex Master-Slave D Flip-FlopPDIP-16648-08NATube25联系BDTIC
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10H176FNGD-Type6ECLECL-5.21.551.50.91900250
MC10H176FNR2GD-Type6ECLECL-5.21.551.50.91900250
MC10H176PGD-Type6ECLECL-5.21.551.50.91900250
Hex D Master-Slave Flip-Flop MC10H176
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
20 LEAD PLLC MC10H351
PDIP-16 MC10H350