MC74ACT377: Octal D Flip-Flop with Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
特性- Ideal for Addressable Register Applications
- Clock Enable for Address and Data Synchronization Applications
- Eight Edge-Triggered D Flip-Flops
- Buffered Common Clock
- Outputs Source/Sink 24 mA
- See MC74AC273 for Master Reset Version
- See MC74AC373 for Transparent Latch Version
- See MC74AC374 for 3-State Version
- ACT377 Has TTL Compatible Inputs
- Pb-Free Packages are Available
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应用注释 (1)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| SOIC-20 WB | 751D-05 (36.3kB) | H |
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| MC74ACT377DWG | Active | Pb-free
Halide free | SOIC-20W | 751D-05 | 3 | Tube | 38 | $0.3467 |
| MC74ACT377DWR2G | Active | Pb-free
Halide free | SOIC-20W | 751D-05 | 3 | Tape and Reel | 1000 | $0.3467 |
订购产品技术参数
| Product | Type | Channels | VCC Min (V) | VCC Max (V) | tpd Max (ns) | IO Max (mA) |
|---|
| MC74ACT377DWG | D-Type | 8 | 4.5 | 5.5 | 10 | 24 |
| MC74ACT377DWR2G | D-Type | 8 | 4.5 | 5.5 | 10 | 24 |
