NB3L8504S: 2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator
The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator with OE control for each differential output. The differential inputs which can be driven by either a differential or single−ended input, can accept various logic level standards such as
LVPECL, LVDS, HSTL, HCSL and SSTL. These signals are then translated to four identical LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is ideal for Clock distribution applications that require low skew.
特性- Four Differential LVDS Outputs
- Each Differential Output has OE Control
- 700 MHz Maximum Output Frequency
- 660 ps Max Output Rise and Fall Times, LVCMOS
- Translates Differential Input to LVDS Levels
- Additive Phase Jitter RMS: < 100 fs Typical
- 50 ps Maximum Output Skew
- 350 ps Maximum Part−to−part Skew
- 1.3 ns Maximum Propagation Delay
- Operating Range: VCC = 2.375 V to 3.630 V
- −40°C to +85°C Ambient Operating Temperature
|
应用- Telecom
- Ethernet
- Networking
- SONET
| 终端产品 |
应用注释 (5)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| TSSOP-16 | 948F-01 (41.7kB) | B |
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB3L8504SDTG | Active | Pb-free
Halide free | TSSOP-16 | 948F-01 | 1 | Tube | 96 | 联系BDTIC |
| NB3L8504SDTR2G | Active | Pb-free
Halide free | TSSOP-16 | 948F-01 | 1 | Tape and Reel | 2500 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB3L8504SDTG | Buffer | 1 | 1:4 | HCSL
SSTL
HSTL
LVPECL
LVDS | LVDS | 2.5
3.3 | 0.07 | 50 | 1.3 | 660 | 700 | |
| NB3L8504SDTR2G | Buffer | 1 | 1:4 | LVPECL
HSTL
LVDS
HCSL
SSTL | LVDS | 3.3
2.5 | 0.07 | 50 | 1.3 | 660 | 700 | |
