NB4L52: 2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination
The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.
特性- Maximum Input Clock Frequency > 4 GHz Typical
- 330 ps Typical Propagation Delay
- 145 ps Typical Rise and Fall Times
- Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
- Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
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应用- High Performance Logic for ATE and Networking
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仿真模型 (1)
封装图纸 (1)
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB4L52MNG | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tube | 123 | 联系BDTIC |
| NB4L52MNR2G | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tape and Reel | 3000 | 联系BDTIC |
订购产品技术参数
| Product | Type | Bits | Input Level | Output Level | VCC Typ (V) | tJitter Typ (ps) | tpd Typ (ns) | tsu Min (ns) | th Min (ns) | trec Typ (ns) | tR & tF Max (ps) | fToggle Typ (MHz) |
|---|
| NB4L52MNG | D-Type | 1 | CMOS
LVDS
ECL
CML | ECL | 3.3
5
2.5 | 1 | 0.4 | 0.1 | 0.05 | 0.4 | 190 | 4000 |
| NB4L52MNR2G | D-Type | 1 | LVDS
ECL
CMOS
CML | ECL | 2.5
3.3
5 | 1 | 0.4 | 0.1 | 0.05 | 0.4 | 190 | 4000 |
