NB7L216: Multi Level Clock/Data Input to RSECL High Gain Receiver/Buffer/ Translator with Internal Termination

The NB7L216 is a differential receiver/driver with high gain output targeted for high frequency applications. The device is functionally equivalent to the NBSG16 but with much higher gain output. This highly versatile device provides 35 dB of gain up to 7 GHz. Inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.The VBB pin is internally generated voltage supply available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs. For all single-ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also re bias AC coupled inputs. When used, decouple VBB via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.

特性
  • High Gain of 35 dB from DC to 7 GHz
  • High IIP3: 0 dB
  • 20 mV Minimum Input Voltage Swing
  • Maximum Input Clock Frequency > 8.5 GHz Typical
  • Maximum Input Data Rate > 12 Gb/s
  • 120 ps Typical Propagation Delay
  • 30 ps Typical Rise and Fall Times
  • RSECL Output Level (400 mV Peak-to-Peak Output),Differential Output Only
  • 50 ohms Internal Input Termination Resistors (temp-coefficient of < 6 m/C)
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
  • VBB ECL Reference Voltage Output
  • Test Equipment First Stage Amplifier
  • Datacommunications Post Amplifier
应用
  • OC-192 Data Buffer
  • High Speed Post Amplifier
  • Test Equipment Front-end Amplifier
应用注释 (8)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB7L216; 2.5 V/3.3 V 12 Gb/s Multi Level Clock/Data Input to RSECL High Gain Receiver/Buffer/ Translator with Internal TerminationNB7L216/D (409kB)6Aug, 2016
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB7L216MNEVB ManualEVBUM2085/D (194.0kB)1
评估板与开发工具
产品状况Compliance简短说明
NB7L216MNEVBActiveMultilevel Clock/Data Input Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB7L216MNGActivePb-free Halide freeQFN-16485G-011Tube123联系BDTIC
NB7L216MNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB7L216MNGSignal Driver11:1ECL TTL LVDS CML CMOSECL3.3 2.50.10.1845850012000
NB7L216MNR2GSignal Driver11:1CMOS ECL LVDS CML TTLECL3.3 2.50.10.1845850012000
NB7L216; 2.5 V/3.3 V 12 Gb/s Multi Level Clock/Data Input to RSECL High Gain Receiver/Buffer/ Translator with Internal Termination (409kB) NB7L216
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing Between LVDS and ECL NB100ELT23L
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
EVBUM2085/D - 194 NB7L216MNEVB
QFN16, 3x3, 0.5P NLSF308