NBSG72A: 2 x 2 Crosspoint Switch, SiGe Differential, 2.5 V / 3.3 V, with Ouput Level Select

The NBSG72A is a high-bandwidth fully differential 2 X 2 crosspoint switch with Output Level Select (OLS) capabilities. This is a part of the GigaComm family of high performance Silicon Germanium products. The device is housed in a low profile 3 X 3 mm 16-pin QFN package.Differential inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS/LVTTL input levels.

特性

Maximum Input Clock Frequency > 7 GHz Typical
Maximum Input Data Rate > 7 Gb/s Typical
200 ps Typical Propagation Delay (OLS = FLOAT)
55/45 ps Typical Rise/Fall Times (OLS = FLOAT)
Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or 800 mV Peak-to-Peak Output)
50 Ω Internal Input Termination Resistors
Single−ended LVECL or LVCMOS/LVTTL Select Inputs (SELA, SELB)
Failure management system to automatically re-route data

应用

Interfacing between standard SDH equipment and DWDM equipment to select which lambda (wavelength) to be transmitted.
Routing reference clocks to SERDES/Framers to support Metro Applications using MULTI-RATE devices
Telecom/Datacom switching
Serial digital video routing
Fanout Buffering
Automatic protection switching
Automatic test protocol to verify the switch system (router) operates
ADSL router

封装

应用注释 (11)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Chips that Rip	AND8068/D (25.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5