NLV74HC165A: 8-Bit Serial or Parallel-Input/Serial Output Shift Register
The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load(bar) input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load(bar) input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.
特性- Output Drive Capability: 10 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2 to 6 V
- Low Input Current: 1 mA
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- Chip Complexity: 286 FETs or 71.5 Equivalent Gates
- Pb-Free Packages are Available*
|
应用注释 (1)
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 具体说明 | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NLV74HC165ADR2G | Active | AEC Qualified
PPAP Capable
Pb-free
Halide free | 8-Bit Serial or Parallel-Input/Serial Output Shift Register | SOIC-16 | 751B-05 | 1 | Tape and Reel | 2500 | $0.2493 |
订购产品技术参数
| Product | Type | Channels | VCC Min (V) | VCC Max (V) | tpd Max (ns) | IO Max (mA) |
|---|
| NLV74HC165ADR2G | Shift Register | 1 | 2 | 6 | 30 | 4 |
