PSD4256G6V Flash在系统可编程(ISP)的外设为8位或16位MCU
The PSD family of memory systems for microcontrollers (MCUs) brings in-systemprogrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU-based applications (8-bit or 16-bit), such as configurable memories, PLD logic, and I/O.
PSD devices integrate an optimized macrocell logic architecture. The macrocell was created
to address the unique requirements of embedded system designs. It allows direct
connection between the system address/data bus, and the internal PSD registers, to
simplify communication between the MCU and other supporting devices.
The PSD family offers two methods to program the PSD Flash memory while the PSD is
soldered to the circuit board: in-system programming (ISP) via JTAG, and in-application
programming (IAP).
PSD4256G6V 特性:
- Dual bank Flash memories
– 8 Mbits of primary Flash memory (16 uniform sectors, 64 Kbytes)
– 512 Kbits of secondary Flash memory with 4 sectors
– Concurrent operation: read from one memory while erasing and writing the other
– 256 kbits of SRAM
– PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select decoding - Seven I/O ports with 52 I/O pins
52 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os
– l/O ports may be configured as open-drain outputs - In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows full-chip in-system programmability
– Efficient manufacturing allow easy product testing and programming
– Use low cost FlashLINK? cable with PC - Page register
– Internal page register that can be used to expand the microcontroller address space by a factor of 256 - Programmable power management
- High endurance
– 100,000 erase/write cycles of Flash memory
– 1,000 erase/write cycles of PLD
– 15 year data retention - Single supply voltage
– 3 V (+20%/–10%) - Memory speed
– 100 ns Flash memory and SRAM access time for VCC = 3 V (+20%/–10%)
– 90 ns Flash memory and SRAM access time for VCC = 3.3 V (+/–10%) - Packages are ECOPACK?
PSD4256G6V 技术支持与电子电路设计开发资源下载
- PSD4256G6V 数据手册DataSheet下载.PDF
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