技术特性

• Core
  • Max fCPU: 24 MHz
  • Advanced STM8A core with Harvard architecture and 3-stage pipeline
  • Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPUfor industry standard benchmark
• Memories
  • Program memory: 32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
  • Data memory: up to 2 Kbytes true data EEPROM; endurance 300 kcycles
  • RAM: 2 Kbytes to 6 Kbytes
• Clock management
  • Low-power crystal resonator oscillator with external clock input
  • Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators
  • Clock security system with clock monitor
• Reset and supply management
  • Wait/auto-wakeup/Halt low-power modes with user definable clock gating
  • Low consumption power-on and power-down reset
• Interrupt management
  • Nested interrupt controller with 32 vectors
  • Up to 37 external interrupts on 5 vectors
• Timers
  • 2 general purpose 16-bit timers with up to 3 CAPCOM channels each (IC, OC, PWM)
  • Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
  • 8-bit AR basic timer with 8-bit prescaler
  • Auto-wakeup timer
  • Window and independent watchdog timers
• I/Os
  • Up to 68 user pins (11 high sink I/Os)
  • Highly robust I/O design, immune against current injection
• Communication interfaces
  • High speed 1 Mbit/s CAN 2.0B interface
  • USART with clock output for synchronous operation - LIN master mode
  • LINUART LIN 2.1 compliant, master/slave modes with automatic resynchronization
  • SPI interface up to 10 Mbit/s or fMASTER/2
  • I²C interface up to 400 Kbit/s
• Analog to digital converter (ADC)
  • 10-bit resolution, 2 LSB TUE, 1 LSB linearity and up to 16 multiplexed channels
• Operating temperature up to 150 °C
• Qualification conforms to AEC-Q100 rev G

功能框图