SN74LV125A-Q1 Quadruple Bus Buffer Gates With 3-State Outputs

SN74LV125A-Q1 描述

The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down

SN74LV125A-Q1
Vcc range(V) 2.0 to 5.5  
Logic True  
Input Level LVTTL  
Output Level LVTTL  
Output Drive(mA) -8,8  
No. of Outputs 4  
Static Current 0.02  
Rating Automotive  
Technology Family LV-A
SN74LV125A-Q1 特性
SN74LV125A-Q1 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74LV125AQRGYRQ1 ACTIVE -40 to 125 0.20 | 1ku VQFN (RGY) | 14 2000 | LARGE T&R  
SN74LV125A-Q1 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74LV125AQRGYRQ1 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LV125AQRGYRQ1 SN74LV125AQRGYRQ1
SN74LV125A-Q1 应用技术支持与电子电路设计开发资源下载
  1. SN74LV125A-Q1 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
  3. CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
  4. Semiconductor Packing Methodology (PDF 3005 KB)
  5. 逻辑产品选择指南 2006/2007 (修订版 Z)(4462KB)
  6. 标准线性和逻辑产品 5 分钟指南 (786KB)
  7. 了解和解释标准逻辑数据表
  8. LOGIC Pocket Data Book (PDF 6001 KB)
  9. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  10. Logic Cross-Reference (PDF 2938 KB)