ADS6124 具有可选并行 CMOS 或 LVDS 输出的低功耗 12 位 105MSPS ADC

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

	ADS6122	ADS6123	ADS6124	ADS6125	ADS6142	ADS6143	ADS6144	ADS6145
Resolution(Bits)	12	12	12	12	14	14	14	14
Sample Rate (max)	65MSPS	80MSPS	105MSPS	125MSPS	65MSPS	80MSPS	105MSPS	125MSPS
Architecture	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline
Power Consumption(Typ)(mW)	285	318	374	417	285	318	374	417
SINAD(dB)	71.5	71.3	71	70.6	74.4	74.3	73.2	72.7
SNR(dB)	71.6	71.5	71.3	71.3	74.6	74.4	74.1	74.1
SFDR(dB)	89	89	83	80	86	89	84	84
DNL(Max)(+/-LSB)	2	2	2	2	0.95	0.95	0.95	0.95
INL(Max)(+/-LSB)	2	2	2	2	3.5	3.5	4.5	4.5
No Missing Codes(Bits)	12	12	12	12	14	14	14	14
ENOB(Bits)	11.6	11.6	11.5	11.4	12	12	11.8	11.7
No. of Supplies	2	2	2	2	2	2	2	2
Analog Voltage AV/DD(Min)(V)	3.0	3.0	3.0	3.0	3.0	3.0	3.0	3.0
Analog Voltage AV/DD(Max)(V)	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
Logic Voltage DV/DD(Min)(V)	3.0	3.0	3.0	3.0	3.0	3.0	3.0	3.0
Logic Voltage DV/DD(Max)(V)	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
Input Configuration Range	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)
Reference Mode	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext	Int and Ext
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Pin/Package	32QFN	32QFN	32QFN	32QFN	32QFN	32QFN	32QFN	32QFN
# Input Channels	1	1	1	1	1	1	1	1
Operating Temperature Range(°C)	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85

ADS6124 特性

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging

ADS6124 芯片订购指南

器件	状态	温度 (oC)	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体
ADS6124IRHB25	ACTIVE	-40 to 85	34.70 \| 100u	QFN (RHB) \| 32	25 \| SMALL T&R
ADS6124IRHBR	ACTIVE	-40 to 85	28.45 \| 100u	QFN (RHB) \| 32	3000 \| LARGE T&R
ADS6124IRHBRG4	ACTIVE	-40 to 85	28.45 \| 100u	QFN (RHB) \| 32	3000 \| LARGE T&R
ADS6124IRHBT	ACTIVE	-40 to 85	29.70 \| 100u	QFN (RHB) \| 32	250 \| SMALL T&R
ADS6124IRHBTG4	ACTIVE	-40 to 85	29.70 \| 100u	QFN (RHB) \| 32	250 \| SMALL T&R