This Evaluation Module (EVM) facilitates the experimental testing of the Texas Instruments SN65LVDS18 Repeater/Translator silicon device. This device accepts low-voltage PECL or LVTTL input levels and translates them to LVDS output levels as defined by TIA/EIA-644-A standard. The device operates at rates to 2.0Gbps or clock rates to 1.0 GHz at either 3.3 V or 2.5 V supply operation, with less than 17 ps of peak C to C jitter.
The device output can be disabled to the high impedance state by applying a logic high level to the EN bar pin. This device also provides a voltage reference output (Vbb) of typically 1.35 V below Vcc for use in receiving single-ended PECL input signals. A Gain Control input (GC), is provided for selecting Output amplitudes from 300mV to 860mV on the /Q output. (When left open, the /Q output defaults to 575mV's.)
| 器件型号 | 名称 | 产品系列 |
| SN65LVDS18 | 具有使能端的 2.5V/3.3V 振荡器增益级/缓冲器 | LVDS/SN65LVDS18/ECL/CML |
