AD1859JR: Stereo, Single-Supply 18-Bit Integrated (Sigma Delta) DAC SOIC-28封装
The AD1859 is a complete 16-/18-bit single-chip stereo digital audio play-back subsystem. It comprises a variable rate digital interpolation filter, a revolutionary multibit sigma-delta modulator with dither, a jitter-tolerant DAC, switched capacitor and continuous time analog filters, and analog output drive circuitry. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port.
The key differentiating feature of the AD1859 is its asynchronous master clock capability. Previous sigma-delta audio DACs required a high frequency master clock at 256 or 384 times the intended audio sample rate. The generation and management of this high frequency synchronous clock is burdensome to the board level designer. The analog performance of conventional single bit sigma-delta DACs is also dependent on the spectral purity of the sample and master clocks. The AD1859 has a digital Phase Locked Loop (PLL) which allows the master clock to be asynchronous, and which also strongly rejects jitter on the sample clock (left/right clock). The digital PLL allows the AD1859 to be clocked with a single frequency (27 MHz for example) while the sample frequency (as determined from the left/right clock) can vary over a wide range. The digital PLL will lock to the new sample rate in approximately 100 ms. Jitter components 15 Hz above and below the sample frequency are rejected by 6 dB per octave. This level of jitter rejection is unprecedented in audio DACs.
The AD1859 supports continuously variable sample rates with essentially linear phase response, and with an option for external analog deemphasis processing. The clock circuit includes an on-chip oscillator, so that the user need only provide an external crystal. The oscillator may be overdriven, if desired, with an external clock source.
The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can be configured in left-justified, I2S-justified, right-justified and DSP serial port compatible modes. The AD1859 accepts 16- or 18-bit serial audio data in MSB-first, twos-complement format. A power-down mode is offered to minimize power consumption when the device is inactive. The AD1859 operates from a single +5 V power supply. It is fabricated on a single monolithic integrated circuit using a 0.6 µM CMOS double polysilicon, double metal process, and is housed in 28-pin SOIC and SSOP packages for operation over the temperature range -40°C to +105°C.
AD1859JR 功能框图
| DAC DNR (dB) | 94dB | Product Description | Stereo, Single Supply 18-bit Integrated Sigma-Delta D/A |
| SNR (dB) | 88dB |
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD1859JR | 量产 | 28 ld SOIC - Wide | 28 | 商业 |
| AD1859JR-REEL | 量产 | 28 ld SOIC - Wide | 28 | 商业 |
| AD1859JRS | 量产 | 28 ld SSOP | 28 | 商业 |
| AD1859JRS-REEL | 量产 | 28 ld SSOP | 28 | 商业 |
| AD1859JRZ | 量产 | 28 ld SOIC - Wide | 28 | 商业 |
| AD1859JRZ-RL | 量产 | 28 ld SOIC - Wide | 28 | 商业 |
