AD9268BCPZ-105: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
The AD9268 is a dual, 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
产品亮点
- On-chip dither option for improved SFDR performance with low power analog input.
- Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.
- Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.
- Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.
- Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products (which is planned for release in May 2009) for lower sample rate, low power applications.
产品应用领域 Applications
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
AD9268BCPZ-105 特点
- SNR = 78.2 dBFS @ 70 MHz
- SFDR = 88 dBc @ 70 MHz
- Low power: 750 mW @ 125 MSPS
- 1.8 V analog supply operation
- 1.8 V CMOS or LVDS output supply
- Integer 1-to-8 input clock divider
- IF sampling frequencies to 300 MHz
- −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
- Optional on-chip dither
- See data sheet for additional features
AD9268BCPZ-105 功能框图
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Complementary Products
- Analog Devices' new low-power ADCs are compatible with ADI's dual-channel VGA (variable gain amplifiers), including the AD8372 programmable dual VGA and AD8376 IF dual VGA as well as the ADL5561 differential RF/IF amplifier and ADL5562 differential RF/IF amplifier.
- For DC-coupled applications, suggested ADC drivers include the ADA4937-2 or ADA4938-2.
- Recommended clock generators include the AD9520-0 and AD9522-0.
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD9268-105EBZ | 量产 | 评估板 | - | 工业 |
| AD9268-125EBZ | 量产 | 评估板 | - | 工业 |
| AD9268-80EBZ | 量产 | 评估板 | - | 工业 |
| AD9268BCPZ-105 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
| AD9268BCPZ-125 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
| AD9268BCPZ-80 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
| AD9268BCPZRL7-105 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
| AD9268BCPZRL7-125 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
| AD9268BCPZRL7-80 | 量产 | LFCSP:LEADFRM CHIP SCALE | 64 | 工业 |
AD9268BCPZ-105 应用技术支持与电子电路设计开发资源下载
- AD9268-125 数据手册DataSheet下载 . pdf
- Analog Devices, Inc.ADI 美国模拟器件公司产品订购手册 .pdf
- ADC模数转换器选型指南 . pdf
