AD9600BCPZ-125 10位、105 MSPS/125 MSPS/150 MSPS、1.8 V双核模数转换器

AD9600BCPZ-125: 10位、105 MSPS/125 MSPS/150 MSPS、1.8 V双核模数转换器

The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9600 has several functions that simplify the automated gain control (AGC) function in a communications receiver. For example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows moni-toring the amplitude of the incoming signal with short latency, using the four fast detect bits of the ADC. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly adjust the system gain to avoid an overrange condition.

Another AGC-related function of the AD9600 is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 10-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. In addition, flexible power-down options allow significant power savings.

AD9600是一款双核、10位、105 MSPS/125 MSPS/150 MSPS ADC,旨在支持要求低成本、小尺寸和多功能特性的通信应用。

这款双核ADC采用多级、差分流水线架构,并集成了输出纠错逻辑。每个ADC均具有宽带宽、差分采样保持模拟输入放大器,支持用户可选的各种输入范围。集成基准电压源可简化设计。占空比稳定器可用来补偿ADC时钟占空比的波动,使转换器保持出色的性能。

AD9600内置多种功能,可以简化通信接收机中的自动增益控制（AGC）功能。例如,快速检测特性可以通过输出四位输入电平信息实现快速检测超量程输入,并且延迟极短。此外,利用ADC的4个快速检测位,可编程阈值检测器可以监控传入信号的波幅,且延迟极短。如果输入信号电平超过可编程阈值,精调阈值上限指示器就会变为高电平。由于此阈值由四个最高有效位（MSB）设置,因此用户可以迅速调整系统增益,以避免发生超量程情况。

AD9600的另一个AGC相关功能是信号监控器。该模块允许用户监控传入信号的复合幅度,这有助于设置增益以优化系统整体的动态范围。

ADC输出数据可以直接路由至两个外部10位输出端口,这些输出可以设置为1.8 V至3.3 V CMOS或1.8 V LVDS。此外,灵活的省电选项可以明显降低功耗。

产品焦点 Product Highlights

Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz.
The AD9600 operates from a single 1.8 V supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down mode, and voltage reference mode.
The AD9600 is pin compatible with the AD9627-11, AD9627, and AD9640 allowing a simple migration from 10 bits to 11 bits, 12 bits, or 14 bits.
集成式双核、10位、150 MSPS/125 MSPS/105 MSPS ADC
快速超量程检测和带串行输出的信号监控器。
具有专用串行输出模式的信号监控器模块。
取得专利的差分输入在最高450 MHz的输入频率下仍保持出色的信噪比（SNR）性能。
AD9600采用1.8 V单电源供电,而数字输出驱动器采用一个独立的电源供电,以适应1.8 V至3.3 V逻辑产品系列。
标准串行端口接口支持各种产品特性和功能,例如：数据格式化（偏移二进制、二进制补码或格雷码）、启用时钟DCS、省电模式以及基准电压模式等。
AD9600与AD9627-11、AD9627和AD9640引脚兼容,使10位产品可轻松升级至11位、12位、或14位产品。

产品应用领域 Applications

点对点无线电接收机（GPSK、QAM）
分集无线电系统
I/Q解调系统
智能天线系统
数字预失真
通用软件无线电
宽带数据应用
数据采集
无损测试

AD9600BCPZ-125 特点

SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
SFDR = 81 dBc to 70 MHz at 150 MSPS
Low power: 825 mW at 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
Integer 1 to 8 input clock divider
Intermediate frequency (IF) sampling frequencies up to 450 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
信噪比（SNR）：60.6 dBc
（61.6 dBFS,至70 MHz、150 MSPS）
无杂散动态范围（SFDR）：
81 dBc（至70 MHz、150 MSPS）
低功耗：825 mW（150 MSPS）
1.8 V模拟电源供电
1.8 V至3.3 V CMOS输出电源或1.8 V LVDS电源
1至8整数输入时钟除法器
中频（IF）采样频率最高可达450 MHz
模数转换器（ADC）内置基准电压源
集成ADC采样保持输入
灵活的模拟输入范围：1 V p-p至2 V p-p
差分模拟输入、650 MHz带宽
ADC时钟占空比稳定器

AD9600BCPZ-125 功能框图

AD9600BCPZ-125 技术指标

Resolution (Bits)	10bit	Interface	Par
T-Put Rate	150MSPS	Ain Range	(2Vref) p-p,1 V p-p,2 V p-p
# Chan	2	SNR (dB)	60.6dB
Supply V	Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig)	Pkg Type	CSP
Pwr Diss (max)	890mW	--	--

AD9600 芯片订购指南

产品型号	产品状态	封装	引脚	温度范围
AD9600-150EBZ	Prodn	EVALUATION BOARDS	64	Comm.
AD9600BCPZ-105	Prodn		64	Comm.
AD9600BCPZ-125	Prodn		64	Comm.
AD9600BCPZ-150	Prodn		64	Comm.

民用温度范围：0 ºC～＋70 ºC
军用温度范围：－55ºC ～＋125ºC
工业用温度范围：不同型号的产品的温度范围可能不同。
汽车工作温度范围：-40 ℃～ +125 ℃