AD9601: 10位、200 MSPS/250 MSPS、1.8 V模数转换器
The AD9601 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.
The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9601 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).
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AD9601是一款10位单芯片采样模数转换器（ADC）,专门针对高性能、低功耗和易用性进行了优化。该产品的转换速率最高可达250 MSPS,具有杰出的动态性能,适合宽带载波和宽带系统使用。芯片上集成了全部必需功能,包括采样保持（T/H）与基准电压源,可提供完整的信号转换解决方案。
该ADC要求采用1.8 V模拟电源供电及差分时钟信号,以便充分发挥其工作性能。数字输出为CMOS兼容,支持二进制补码、偏移二进制或格雷码格式。该ADC还提供数据时钟输出,用于正确进行输出数据定时。AD9601采用先进的CMOS工艺制造,提供56引脚LFCSP封装,额定温度范围为-40°C至+85°C工业温度范围。
AD9601 特点
- SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS
- ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
- SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
- Excellent linearity
DNL = 0.2 LSB typical
INL = 0.2 LSB typical - CMOS outputs
Single data port at up to 250 MHz
Demultiplexed dual port at up to 2 × 125 MHz - 700 MHz full power analog bandwidth
- On-chip reference, no external decoupling required
- Integrated input buffer and track-and-hold
- Low power dissipation
274 mW @ 200 MSPS
322 mW @ 250 MSPS - Programmable input voltage range
- 1.0 V to 1.5 V, 1.25 V nominal
- 1.8 V analog and digital supply operation
- Selectable output data format (offset binary, twos complement, Gray code)
- 信噪比（SNR）：59.4 dBFS （fIN最高为70 MHz,250 MSPS）
- ENOB：9.7 （fIN最高为70 MHz,250 MSPS,−1.0 dBFS）
- 无杂散动态范围（SFDR）：81 dBc （fIN最高为70 MHz,250 MSPS,−1.0 dBFS）
- 出色的线性度：
微分非线性（DNL）= 0.2 LSB（典型值）
积分非线性（INL）= 0.2 LSB（典型值） - CMOS输出
单数据端口最高可达250 MHz
解复用双端口最高可达2 × 125 MHz - 700 MHz全功率模拟带宽
- 片内基准电压源,无需外部解耦
- 集成输入缓冲和采样保持
- 低功耗
274 mW（200 MSPS）
322 mW（250 MSPS） - 可编程输入电压范围1.0 V至1.5 V,1.25 V（标称值）
- 采用1.8 V模拟和数字电源供电
- 可选择输出数据格式 （偏移二进制、二进制补码、格雷码）
AD9601 亮点
- High Performance–Maintains 59.4 dBFS SNR @ 250 MSPS with a 70 MHz input.
- Low Power–Consumes only 322 mW @ 250 MSPS.
- Ease of Use–CMOS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.
- Serial Port Control–Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation.
- Pin-Compatible Family–12-bit pin-compatible family offered as the AD9626
- 高性能：信噪比维持在59.4 dBFS（250 MSPS、70 MHz输入）。
- 低功耗：仅322 mW（250 MSPS）。
- 易于使用：CMOS输出数据和输出时钟信号允许与现行FPGA接口。片内基准电压源和采样保持功能使系统设计更灵活。采用1.8 V单电源则简化了系统电源设计
- 串行端口控制：标准串行端口接口支持各种产品功能,例如：数据格式化、省电模式、增益调整及生成输出测试图样等。
- 引脚兼容系列：如12位引脚兼容系列产品AD9626。
AD9601 技术指标
- Resolution (Bits): 10bit
- # Chan: 1
- Sample Rate: 250MSPS
- Interface: Par
- Analog Input Type: Diff-Uni
- Ain Range: 1 V p-p,1.25 V p-p,1.5 V p-p
- ADC Architecture: Pipelined
- Pkg Type: CSP
AD9601 应用领域
- 无线和有线宽带通信
- 电缆反转通路
- 通信测试设备
- 雷达和卫星子系统
- 功率放大器线性化
AD9601 功能框图
AD9601 芯片订购指南
| 产品型号 | 产品状态 | 封装 | Pins | 温度范围 |
|---|---|---|---|---|
| AD9601-250EBZ | Prodn | EVALUATION BOARDS | 56 | Ind |
| AD9601BCPZ-200 | Prodn | LFCSP:LEADFRM CHIP SCALE | 56 | Ind |
| AD9601BCPZ-250 | Prodn | LFCSP:LEADFRM CHIP SCALE | 56 | Ind |
