ADN2811ACP-CML-RL: Dual Rate Limiting Amplifier and Clock and Data Recovery IC
The ADN2811 provides receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-48 and the associated FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for -40ºC to +85ºC ambient temperature unless otherwise noted.
The proprietary delay and phase-locked loop design of the ADN2811 provides unprecedented jitter performance for robust high-speed networking designs.
The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip crystal oscillator. Both native rates and 15/14 rate digital wrappers rates are supported by the ADN2811, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold.
ADN2811ACP-CML-RL 特点
- Dual rate 2.5/2.7Gbps
- Integrated Limiting Amplifier with Adjustable Slice
- Quantizer Sensitivity: 6 mV
- Adjustable Slice Level: ±100 mV
- Exceeds all SONET/SDH Requirements for Jitter Transfer, Generation, and Tolerance
- Internal MUX to Bypass CDR
- Low power: 540 mW
- One supply: 3.0V - 3.6V
- Single Reference Clock Frequency for All Rates
- Loss-of-Lock Indicator
- Small Footprint: 48-lead LFCSP Package (7 mm x 7 mm overall)
ADN2811ACP-CML-RL 功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| ADN2811ACP-CML | 量产 | 48 ld LFCSP 7x7mm (5.25EP) | 48 | 商业 |
| ADN2811ACP-CML-RL | 量产 | 48 ld LFCSP 7x7mm (5.25EP) | 48 | 商业 |
| ADN2811ACPZ-CML | 量产 | 48 ld LFCSP 7x7mm (5.25EP) | 48 | 工业 |
