ADN2817ACPZ-RL

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.

The ADN2817/ADN2818 have many optional features available through an I²C® interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.

The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.

产品应用领域 Applications
ADN2817ACPZ-RL 特点
ADN2817ACPZ-RL 功能框图

ADN2817 芯片订购指南
产品型号 产品状态 封装 引脚 温度范围
ADN2817ACPZ 量产 32 ld LFCSP (5x5mm CP-32-2) 32 商业
ADN2817ACPZ-RL 量产 32 ld LFCSP (5x5mm CP-32-2) 32 工业
ADN2817ACPZ-RL7 量产 32 ld LFCSP (5x5mm CP-32-2) 32 工业
EVAL-ADN2817EBZ 量产 评估板 - 工业
ADN2817ACPZ-RL 应用技术支持与电子电路设计开发资源下载
  1. ADN2817 数据手册DataSheet 下载 . pdf
  2. ADI 模拟器件公司比较器产品选型指南 . pdf
  3. Analog Devices, Inc. 美国模拟器件公司产品订购手册 .pdf