ADSP-TS101S 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

ADSP-TS101S: 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

ADSP-TS101S 功能框图 The ADSP-TS101S is the first member of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI’s TigerSHARC processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS101S features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC processor to offer unrivaled DSP performance. At a 300 MHz clock rate, the ADSP-TS101S offers the industry’s highest 16-bit fixed-point performance and a 32-bit floating 1024-point complex FFT time of 32.5 microseconds.

ADSP-TS101S Performance:

High performance 300 MHz, 3.3 ns instruction rate DSP core
Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle
Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (1800 MFLOPS or 7.2 GOPS performance)
8-cycle instruction pipeline; 3-cycle fetch pipe and 5-cycle execution pipe
Parallelism allows the execution of up to four 32-bit instructions per cycle

The ADSP-TS101S is available in both 19mm X 19mm and 27mm X 27mm inexpensive, plastic ball-grid array packages. The TigerSHARC is available for general purpose sampling today.

技术特性

Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
High performance 300 MHz, 3.3 ns instruction rate DSP core
6 Mbit on-chip SRAM internally organized in three banks with user-defined partitioning
14 channel, zero overhead DMA controller
Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC to offer complete base band processing
Three internal 128-bit wide internal buses providing a total memory bandwidth of 14.4 Gbytes per second
Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
Assembly and C language programmability

技术指标

Clock Speed (MHz): 300MHz
MMACs: 2400
On-Chip Memory (Mbit): 6Mbit
External Memory (Mbit): 32/64
Parallel Bus: Yes
Core Voltage (V): 1.2V
Package: 19 x 19 BGA,27 x 27 BGA

市场与应用

Video and communications markets including the 3G cellular and 802.16 broadband wireless base stations
Industrial and Instrumentation including military and medical

订购指南

产品型号		引脚	温度范围	包装和数量	报价*(100-499)	报价*1000 pcs	RoHS
ADSP-TS101SAB1-000 产品状态: 量产	625 ball BGA	625	工业	Tray, 40	$ 237.28	$ 217.41	否
ADSP-TS101SAB1-100 产品状态: 量产	625 ball BGA	625	工业	Tray, 40	$ 282.86	$ 259.49	否
ADSP-TS101SAB1Z000 产品状态: 量产	625 ball BGA	625	工业	Tray, 40	$ 211.60	$ 193.88	是
ADSP-TS101SAB1Z100 产品状态: 量产	625 ball BGA	625	工业	Tray, 40	$ 252.25	$ 231.40	是
ADSP-TS101SAB2-000 产品状态: 量产	484 ball BGA	484	工业	Tray, 84	$ 237.28	$ 217.41	否
ADSP-TS101SAB2-100 产品状态: 量产	484 ball BGA	484	工业	Tray, 84	$ 282.86	$ 259.49	否
ADSP-TS101SAB2Z000 产品状态: 量产	484 ball BGA	484	工业	Tray, 84	$ 211.60	$ 193.88	是
ADSP-TS101SAB2Z100 产品状态: 量产	484 ball BGA	484	工业	Tray, 84	$ 252.25	$ 231.40	是

开发工具

产品型号	封装	引脚	温度范围	包装和数量	报价*(100-499)	报价*1000 pcs	RoHS
ADZS-TS201S-EZLITE 产品状态: 量产	评估板	-	待定	1	$ 1,000.00	$ 1,000.00	是
ADZU-TS201S-EZLITE 产品状态: 量产	评估板	-	待定	1	-	-	是

ADSP-TS101S 应用技术支持与电子电路设计开发资源下载

ADSP-TS101S 数据手册DataSheet 下载 . pdf
ADI 模拟器件公司比较器产品选型指南 . pdf
Analog Devices, Inc. 美国模拟器件公司产品订购手册 .pdf
ADSP-TS101 硬件技术手册 .pdf
ADSP-TS101 编程技术手册 .pdf
ADSP-TS201 硬件技术手册 .pdf
ADSP-TS201 编程技术手册 .pdf