技术特性

• Receiver:
  
  • On chip Clock and Data Recovery circuit for high input jitter tolerance
    
  • Meets the jitter tolerance requirements as specified in ITU-T G.823_1993 for E3 and Telcordia GR-499-CORE for DS3 applications
    
  • Detects and Clears LOS as per G.775
    
  • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation
    
  • On chip B3ZS/HDB3 encoder and decoder that can either be enabled or disabled
    
  • On-chip clock synthesizer generates the appropriate rate clock from a single frequency XTAL
    
  • Provides low jitter clock outputs for either DS3, E3 or STS-1 rates
    
  • On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock
    
  • Provides low jitter output clock
  Transmitter:
  
  • Compliant with Bellcore GR-499, GR-253 and ANSI T1.102 Specification for transmit pulse
    
  • Tri-state Transmit output capability for redundancy applications
    
  • Transmitter can be turned on or off
  Control and Diagnostics:
  
  • 5 wire Serial Microprocessor Interface for control and configuration
    
  • Supports optional internal Transmit Driver Monitoring
    
  • PRBS error counter register to accumulate errors
    
  • Hardware Mode for control and configuration
    
  • Supports Local, Remote and Digital Loop-backs
    
  • Single 3.3 V ± 5% power supply
    
  • 5V Tolerant I/O
    
  • Available in 100 pin TQFP
    
  • -40°C to 85°C Industrial Temperature Range
    
  • Pb-Free, RoHS Compliant Versions Offered

技术指标

应用领域 APPLICATION

• E3/DS3 Access Equipment
  
• STS1-SPE to DS3 Mapper
  
• DSLAMs
  
• Digital Cross Connect Systems
  
• CSU/DSU Equipment
  
• Routers
  
• Fiber Optic Terminals

订购信息 Ordering Information

功能框图 Functional Block Diagram