技术特性

• Receiver:
  
  • On-chip Clock and Data Recovery circuit for high input jitter tolerance
    
  • Meets E3/DS3/STS-1 Jitter Tolerance Requirements
    
  • Detects and Clears LOS as per G.775
    
  • Meets Bellcore GR-499 CORE Jitter Transfer Requirements
    
  • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation
    
  • Compliant with jitter transfer template outlined in ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards
    
  • Meets ETSI TBR 24 Jitter Transfer Requirements
    
  • On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled
    
  • On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock
    
  • Provides low jitter output clock
  Transmitter:
  
  • Compliant with Bellcore GR-499, GR-253 and ANSI T1.102 Specification for transmit pulse
    
  • Tri-state Transmit output capability for redundancy applications
    
  • Transmitter can be turned on or off
  Jitter Attenuator:
  
  • On chip advanced crystal-less Jitter Attenuator
    
  • Jitter Attenuator can be selected in Receive or Transmit paths
    
  • 16 or 32 bits selectable FIFO size
    
  • Meets the Jitter and Wander specifications described in T1.105.03b,ETSI TBR-24, Bellcore GR-253 and GR-499 standards
    
  • Jitter Attenuator can be disabled
  Control and Diagnostics:
  
  • 5 wire Serial Microprocessor Interface for control and configuration
    
  • Supports optional internal Transmit Driver Monitoring
    
  • PRBS error counter register to accumulate errors
    
  • Hardware Mode for control and configuration
    
  • Supports Local, Remote and Digsital Loop-backs
    
  • Single 3.3 V ± 5% power supply
    
  • 5 V Tolerant I/O
    
  • Available in 52-pin TQFP
    
  • -40°C to 85°C Industrial Temperature Range
    
  • Pb-Free, RoHS Compliant Versions Offered

技术指标

应用领域 APPLICATION

• E3/DS3 Access Equipment
  
• DSLAMs
  
• Digital Cross Connect Systems
  
• CSU/DSU Equipment
  
• Routers
  
• Fiber Optic Terminals

订购信息 Ordering Information

功能框图 Functional Block Diagram