技术特性

• Provides DS3/ E3 mapping/demapping for up to 3 tributaries through SONET STS-1 or SDH AU-3 and/or TUG-3/AU-4 containers
  
• Generates and terminates SONET/SDH section, line and path layers
  
• Integrated SERDES with Clock Recovery Circuit
  
• Provides SONET frame scrambling and descrambling
  
• Integrated Clock Synthesizer that generates 155 MHz and 77.76 MHz clock from an external 12.96/ 19.44/77.76 MHz reference clock
  
• Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit that de-jitter gapped clock to meet 0.05UIpp jitter requirements
  
• Access to Line or Section DCC
  
• Level 2 Performance Monitoring for E3 and DS3
  
• Supports mixing of STS-1E and DS3 or E3 and DS3 tributaries
  
• E3 and DS3 framers for both Transmit and Receive directions
  
• Complete Transport/Section Overhead Processing and generation per Telcordia and ITU standards
  
• Full line APS support for redundancy applications
  
• Loopback support for both SONET/SDH as well as E3/DS3/STS-1
  
• Boundary scan capability with JTAG IEEE 1149
  
• 8-bit microprocessor interface
  
• 3.3V ± 5% Power Supply; 5V input signal tolerance
  
• -40°C to +85°C Operating Temperature Range
  
• Available in a 504 Ball TBGA package
  
• Pb-Free, RoHS Compliant Versions Offered

技术指标

应用领域 APPLICATION

• Network switches
  
• Add/Drop Multiplexer
  
• W-DCS Digital Cross Connect Systems

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