HMC983LP5E Fractional-N Divider and Frequency Sweeper
The HMC983LP5E is a SiGe BiCMOS low noise programmable frequency divider in a 3x3 mm leadless surface mount package. The circuit can be programmed to divide from N = 1 to N = 4 in the 400 MHz to 6 GHz input frequency range. The high level output power (up to 6 dBm single ended) with a very low SSB phase noise and 50% duty cycle makes this device ideal for low noise clock generation, LO generation and LO drive applications. Configurable bias and output power controls allow current consumption and output power control. The device incorporates a power down feature, good input to output isolation and fast start up time. The HMC983LP5E can be included into fast switching "ping-pong" applications.
技术特性
- Wideband: DC - 7 GHz Input
-20-bit Frequency Divider
- Low Noise: -160 dBc/Hz
- Low Spurious: Largest Spurious
- 95 dBc
- 48-bit 100 MHz Delta-Sigma
Modulator (DSM)
- Configurable DSM Size
- Programmable Seed
- Integrated Frequency Sweeper
- Linear, Coherent Sweeps
- 2-Way, 1-Way, & User Defined
Sweep Modes
- Automatic or Triggered
- Programmable Seed
- SPI & External Triggering
- 5-GPIO's, can be used for
External DSM
- Cycle Slip Prevention Support
with PFD Chip(HMC984LP4E)
- Differential VCO Input &
Divider Output
- Programmable Output
Current Control:
-5 mA to 17.5 mA Open Collector
Output Driver
- 32 Lead 5x5mm SMT Package:
25mm
|
技术指标
| Input Freq. (GHz) |
Function |
Input Power (dBm) |
Output Level |
Floor FOM (dBc/Hz) |
Bias Supply |
Package |
| DC - 7 |
48-Bit Delta Sigma Programmable
Fractional Divider with Sweeper |
-15 to -3 |
0.75 Vp-p to 2 Vp-p into 100 Ohm |
-160 |
+5V @ 1mA
+3V @ 244mA |
LP5 |
订购信息 Ordering Information
应用领域 APPLICATION
功能框图 Functional Block Diagram
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