The IP100A is a single-chip, full duplex, 10/100Mbps Ethernet MAC + PHY incorporating a 32-bit PCI with bus master support. The IP100A is designed for use in a variety of applications including workstation NICs, PC motherboards, and other systems utilizing a PCI bus that require network connectivity to an Ethernet or Fast Ethernet LAN.
The IP100A includes a PCI bus interface unit, IEEE 802.3 compliant MAC, transmit and receive FIFO buffers, IEEE 802.3 compliant 100BASE-TX, 10BASE-T, and 100BASE-FX PHY, serial EEPROM interface, expansion ROM interface, and LED drivers.
The IP100A implements a rich set of control and status registers. Accessible via the PCI interface, these registers provide a host system visibility into the features and operating state of the IP100A. Network management statistics are also recorded, and host access to registers of the PHY device are facilitated through the IP100A's PCI interface.
The IP100A supports features for use in "Green PCs" or systems where control over system power consumption is desired. The IP100A supports several power down states, and the ability to issue a system "wake event" via reception of unique, user defined Ethernet frames. In addition, the IP100A can assert a wake event in response to changes in the Ethernet link status
