Intel® MCS 96 microcontroller family of products are popular for 16-bit embedded microcontrollers. The 8XC196 products are found in a variety of embedded applications. The high-performance register to register architecture is well suited for complex real-time control applications such as hard disk drives, modems, printers, pattern recognition and motor control. Our broad portfolio of 8XC196 microcontroller products has been designed to meet your varying peripheral, memory size, addressability and performance requirements.
The 8XC196 family shares a common core architecture which is register based. The MCS 96 microcontroller register architecture eliminates the accumulator bottleneck and enables fast context switching. All devices have bit, byte, word and some 32-bit operations. The table below summarizes the capture and generation of high speed signals on the HSIO and EPA.
|OPERATION||16 MHz||20 MHz||25 MHz||50 MHz|
|HSI (High speed input)||1.125 us||900 ns|
|HSO (High speed output)||1 us||800 ns|
|EPA (Event processor array)||250 ns||200 ns||160 ns||80 ns|
The 8XC196 Bus Controller features programmable wait state generation. 8- or 16-bit bus width and features a HOLD/HLDA protocol for multiprocessor systems. The 8XC196NP/NU have dynamically selectable multiplexed/demultiplexed bus and a chip select unit.
The MCS 96 microcontroller product family has three distinct product lines. The most recent products form the EPA Family. This family of devices has the advanced peripherals which include a flexible input/output system and EPA (Event Processor Array). The HSIO Family consists of devices that have the High Speed Input/Output sub-system. The Motor Control Family is comprised of devices that support motor control applications. This family also uses the EPA system for I/O control.
The newest addition to this product line is the CAN + Flash microcontroller, 88CO196EC. This product contains a highly integrated set of functions including Flash and CAN2.0.
|On-chip memory||Low cost - Cost-effective solution|
|Register-to-register architecture||Efficient - More compact code than accumulator-based architecture, which allows more efficient use of memory Unlimited usage - Minimum of 232 registers can be directly addressed at any time|
|Three operand instructions||Create efficient code - Preserve the source data|
|Bus controller features programmable wait-state generation and 8- or 16-bit bus widths||Economical - Efficient usage of wide variety of memory and peripheral devices|
|Flat addressability of large register files||Fewer barriers - Avoids artificial limitation of barriers of segmented files|
|Three distinct product lines:
- Event Processor Array
- High Speed Input/Output
- Motor Control
|Advanced - Peripherals include configurable input/output ports and modular event processor array structure
Speed - Devices with high-speed input FIFO and output system
Waveform - Uses waveform generator and event processor array system for input/output