MC100EL29:5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset
The MC100EL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
技术特性
- 1100 MHz Flip-Flop Toggle Frequency
- 580 ps Propagation Delays
- ESD Protection: > 2 kV HBM, > 100 V MM
- Q Output will Default LOW with Inputs Open or at VEE
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
- Flammability Rating: UL-94 code V-0 @ 0.125 in, Oxygen Index 28 to 34
- Transistor Count = 313 devices
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100EL29DWG |
Active |
|
5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset |
SOIC-20W |
751D-05 |
3 |
Tube |
38 |
|
| MC100EL29DWR2G |
Active |
|
5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset |
SOIC-20W |
751D-05 |
3 |
Tape and Reel |
1000 |
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数据资料DataSheet下载
