MC100LVEP14:2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
特性
- 400 ps Typical Propagation Delay
- 100 ps Device-to-Device Skew
- 25 ps Within Device Skew
- Maximum Frequency > 2 GHz Typical
- The 100 Series Contains Temperature Compensation
- PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
- Open Input Default State
- These are Pb-Free Devices
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封装图 PACKAGE DIMENSIONS
![MC100LVEP14封装图](/image/on/TSSOP-20_PACKAGE_DIMENSIONS.jpg)
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订购信息 Ordering Information
产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价) |
类型 |
外形 |
类型 |
数量 |
MC100LVEP14DT |
Active, Not Rec |
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2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
TSSOP-20 |
948E-02 |
1 |
Tube |
75 |
|
MC100LVEP14DTG |
Active |
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2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
TSSOP-20 |
948E-02 |
1 |
Tube |
75 |
|
MC100LVEP14DTR2 |
Active, Not Rec |
|
2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
TSSOP-20 |
948E-02 |
1 |
Tape and Reel |
2500 |
|
MC100LVEP14DTR2G |
Active |
|
2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer |
TSSOP-20 |
948E-02 |
1 |
Tape and Reel |
2500 |
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