MC10E150:ECL 6-Bit D Latch

The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.

技术特性
  • 800ps Max. Propagation Delay
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 1 kV HBM, > 75 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 173 devices
  • Pb-Free Packages are Available
封装图 MARKING DIAGRAM

MC10E150 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
MC10E150FNG Active
Pb-free
Halide free
ECL 6-Bit D Latch PLCC-28 776-02 3 Tube 37  
MC10E150FNR2G Active
Pb-free
Halide free
ECL 6-Bit D Latch PLCC-28 776-02 3 Tape and Reel 500  
数据资料DataSheet下载
概述 文档编号/大小 版本
ECL 6-Bit D Latch MC10E150-D(417.0kB) 1