MC74HC112A:Dual J-K Flip-Flop with Set and Reset

High Performance Silicon Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has active low asynchronous Set and Reset inputs. The HC112A is identical in function to the HC76, but has a different pinout..

技术特性
  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously
  • Chip Complexity: 100 FETs or 25 Equivalent Gates
  • PbFree Packages are Available
封装图 MARKING DIAGRAM

MC74HC112A 封装图

订购信息 Ordering Information
产品 状况 Compliance 具体说明 封装 MSL* 容器 预算价格 (1千个数量的单价)
类型 外形 类型 数量
MC74HC112ADG Active
Pb-free
Halide free
Dual J-K Flip-Flop with Set and Reset SOIC-16 751B-05 1 Tube 48 $0.104
MC74HC112ADR2G Active
Pb-free
Halide free
Dual J-K Flip-Flop with Set and Reset SOIC-16 751B-05 1 Tape and Reel 2500 $0.104
MC74HC112ADTG Active
Pb-free
Halide free
Dual J-K Flip-Flop with Set and Reset TSSOP-16 948F-01 1 Tube 96 $0.104
MC74HC112ADTR2G Active
Pb-free
Halide free
Dual J-K Flip-Flop with Set and Reset TSSOP-16 948F-01 1 Tape and Reel 2500 $0.104
数据资料DataSheet下载
概述 文档编号/大小 版本
Dual J-K Flip-Flop with Set and Reset MC74HC112A-D(417.0kB) 1