特性

• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• +/- 10% Guaranteed Pulse Width Variation from Part to Part (Using the Same Test Jig)
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 145 FETs or 36 Equivalent Gates
• Pb-Free Packages are Available*

封装图 MARKING DIAGRAM