NB6L11MMNGEVB:EVAL BOARD NB6L11MMNG
The NB6L11M is a differential 1:2 CML fanout buffer. The differential inputs incorporate internal 50-ohm termination resistors that are accessed through the VT pins and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single-ended PECL or NECL inputs. For all single-ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor-coupled inputs. When used, decouple VREFAC with a 0.01uF capacitor and limit current sourcingor sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L11M is a member of the ECLinPS MAX family of high performance clock products.
特性
- Guaranteed Input Clock Frequency up to 1.0 GHz
- Guaranteed Input Data Rate up to 1.5 Gb/s
- 490 ps Maximum Propagation Delay
- 1.0 ps Maximum RMS Jitter
- 180 ps Maximum Rise/Fall Times
- Single Power Supply; VCC = 3.3 V 10%
- Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs
- GND + 50 mV to VCC - 50 mV VCMR Range
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NB6L11MMNGEVB 实物图
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评估板信息
| 评估板 |
状况 |
无铅(Pb-free) |
简短说明 |
所用产品 |
| NB6L11MMNGEVB |
Active |
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NB6L11MMNGEVB:EVAL BOARD NB6L11MMNG |
NB6L11MMNG |
技术文档
| 类型 |
文档标题 |
文档编号 |
修订号 |
| Eval Board: Manual |
NB6L11MMNGEVB Evaluation Board User's Manual |
EVBUM2168/D |
2 |
